There’s one critical mistake the engineers frequently make when designing a crystal oscillator circuit: selecting the right load capacitance (aka CL). This mistake could easily cause RF hardware to fail strict frequency accuracy requirements.
The first step in designing a crystal oscillator circuit is to look at the requirements given by the chip that the crystal interfaces with. Let’s say, for example, you’re designing a 2.4 GHz RF transceiver. The transceiver datasheet requires a 20 MHz crystal with a load capacitance of 10 pF.
The next step is to browse through Digi-key for a 20 MHz crystal that has a load capacitance within the range specified by the datasheet and to make sure it meets other requirements such as tolerance, stability, and ESR.
Ok, so you selected a crystal that listed 10 pF load capacitance on the datasheet. You picked a clock with 10 ppm frequency tolerance and 10 ppm stability over temperature, just to be sure the clock is very accurate. Great choice!
The next step is where the critical mistake often occurs. Figure 1 shows a typical parallel resonant crystal circuit with a capacitor on each crystal pin, connected to ground.
The crystal datasheet says you need a load capacitance of 10 pF, so C1 and C2 should both be 10 pF, right?
Wrong. You’ve payed extra for the accurate crystal, but your clock may not going to be as accurate as you had hoped.
The load capacitance is not the value of each individual capacitance, but rather the total equivalent capacitance in the circuit. Redrawing the circuit with the ground node hidden (Figure 2), it becomes more obvious that C1 and C2 are in series. There’s also an unknown amount of stray capacitance in the circuit. The stray capacitance depends on the chip itself, as well as the layout of the circuit. 3-6 pF is fairly typical. I’ve read the rule of thumb is to assume 5 pF, but I have empirical results in at least one instance where assuming 3 pF stray capacitance resulted in the most accurate clock.
The equation for load capacitance is:
CL = (C1*C2)/(C1+C2) + CSTRAY
Because C1 and C2 are going to be the same value:
CL = C1/2 + CSTRAY
The goal is to get the total capacitance equal to the load capacitance listed on the crystal datasheet, but the stray capacitance is not easily measureable. If you don’t have the test equipment, then the best you may be able to do is make an assumption on stray capacitance.
If you have the right test equipment, then you’ll get the most accurate clock by adjusting C1 and C2 until your clock is as close as possible to the 20 MHz mark.
I’ve successfully tuning an oscillator by using a spectrum analyzer. In this example, I started with a 20 MHz capacitor that required 10 pF load capacitance. C1 and C2 were mistakenly selected to be 10 pF. The resulting frequency, captured in Figure 3, was 20.001523 MHz.
That doesn’t look so bad; however, that’s 76 ppm away from 20 MHz.
ppm = (20.001523-20)/20 x 10^6
This crystal generates the RF frequency for a Zigbee device, which requires an accuracy of 40 ppm over the range of temperature, and over the life of the part. Allowing for 10 ppm due to temperature swings, 10 ppm of tolerance, and 10 ppm of drift over a few years, we need to be much more accurate.
Adjusting the 2 capacitors higher will adjust the frequency down. After trying out a few different values, we found that 14 pF for C1 and C2 provided a very accurate clock. The measurement taken with the spectrum analyzer, captured in figure 4, shows that the clock was 1 ppm off.
Plugging the new values for C1 and C2, and 10 pF as the load capacitance into the load capacitance equation, we find that stray capacitance was equal to ~3 pF in this example.
If your application does not require such a degree of accuracy, feel free to make assumptions about stray capacitance. If your product has strict requirements, you are better off tuning the circuit and measuring the results.